Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog, 6th Edition Solution Manual

1 SOLUTIONS MANUAL PART 1: CHAPTERS 1-5 Rev 10/02/2018 DIGITAL DESIGN WITH AN INTRODUCTION to the VERILOG HDL, VHDL, and SystemVerilog Sixth Edition M. MORRIS MANO Professor Emeritus California State University, Los Angeles MICHAEL D. CILETTI Professor Emeritus University of Colorado, Colorado Springs Note: Solutions to problems requiring HDL code are presented in Verilog and VHDL .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 2 CHAPTER 1 1.1 Base-10: 14 15 16 Octal: 16 17 20 Hex: 10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 40 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Base-10: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Base-12 8 9 0A 0B 10 11 12 13 14 15 16 17 18 19 1A 1B 20 21 22 23 24 1.2 (a) 32,768 (b) 67,108,864 (c) 6,871,947,674 1.3 (4310)5 = 4 * 53 + 3 * 52 + 1 * 51 = 58010 (198)12 = 1 * 122 + 9 * 121 + 8 * 120 = 26010 (445)8 = 4 * 82 + 4 * 81 + 5 * 80 = 29310 (345)6 = 3 * 62 + 4 * 61 + 5 * 60 = 13710 1.4 16-bit binary: 1111_1111_1111_1111 Decimal equivalent: 216 -1 = 65,53510 Hexadecimal equivalent: FFFF16 1.5 Let b = base (a) 14/2 = (b + 4)/2 = 5, so b = 6 (b) 56/4 = (5*b + 6)/4 = 15 = 1*b + 5, so 5*b + 6 = 4*(1*b + 5) = 4*b + 20 so b = 14 (c) 32 + 12 = 28, 3*b + 2 + 1*b + 2 = 2*b + 8 4*b + 4 = 2*b + 8, 2*b = 4, so b = 2 1.6 (x – 3)(x – 6) = x2 –(6 + 3)x + 6*3 = x2 -11x + 22 Therefore: 6 + 3 = b + 1, so b = 8 Also, 6*3 = (18)10 = (22)8 1.7 64CD16 = 0110_0100_1100_11012 = 110_010_011_001 _101 = (62315 )8 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 3 1.8 (a) Results of repeated division by 2 (quotients are followed by remainders): 43110 = 215(1); 107(1); 53(1); Answer: 1111_10102 = FA16 26(1); 13(0); 6(1) 3(0) 1(1) (b) Results of repeated division by 16: 43110 = 26(15); 1(10) (Faster) Answer: FA = 1111_1010 1.9 (a) 10110.01012 = 16 + 4 + 2 + .25 + .0625 = 22.3125 (b) 16.516 = 16 + 6 + 5*(.0615) = 22.3125 (c) 26.248 = 2 * 8 + 6 + 2/8 + 4/64 = 22.3125 (d) DABA.B16 = 13*163 + 10*162 + 11*16 + 10 + 11/16 = 55,994.6875 (e)1011.10012 = 8 + 2 + 1 + .5 + .0625 = 11.5625 1.10 (a) 1.100102 = 0001.10012 = 1.916 = 1 + 9/16 = 1.56310 (b) 110.0102 = 0110.01002 = 6.416 = 6 + 4/16 = 6.2510 Reason: 110.0102 is the same as 1.100102 shifted to the left by two places. 1.11 1011.11 101 | 111011.0000 101 01001 101 1001 101 1000 101 0110 The quotient is carried to two decimal places, giving 1011.11 Checking: 1110112 / 1012 = 5910 / 510 ≅ 1011.112 = 58.7510 1.12 (a) 10000 and 110111 1011 1011 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 4 +101 10000 = 1610 x101 1011 1011 110111 = 5510 (b) 62h and 958h 2Eh 0010_1110 +34 h 0011_0100 62h 0110_0010 = 9810 1.13 2Eh x34h B38 2 8A 9 5 8h = 239210 (a) Convert 27.315 to binary: 27/2 = 13/2 6/2 3/2 ½ Integer Remainder Coefficient Quotient 13 + ½ a0 = 1 6 + ½ a1 = 1 3 + 0 a2 = 0 1 + ½ a3 = 1 0 + ½ a4 = 1 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 5 2710 = 110112 Integer .315 x 2 = 0 .630 x 2 = 1 .26 x 2 = 0 .52 x 2 = 1 Fraction Coefficient + .630 a-1 = 0 + .26 a-2 = 1 + .52 a-3 = 0 + .04 a-4 = 1 .31510 ≅ .01012 = .25 + .0625 = .3125 27.315 ≅ 11011.01012 (b) 2/3 ≅ .6666666667 Integer .6666_6666_67 x 2 = 1 .3333333334 x 2 = 0 .6666666668 x 2 = 1 .3333333336 x 2 = 0 .6666666672 x 2 = 1 .3333333344 x 2 = 0 .6666666688 x 2 = 1 .3333333376 x 2 = 0 Fraction Coefficient + .3333_3333_34 a-1 = 1 + .6666666668 a-2 = 0 + .3333333336 a-3 = 1 + .6666666672 a-4 = 0 + .3333333344 a-5 = 1 + .6666666688 a-6 = 0 + .3333333376 a-7 = 1 + .6666666752 a-8 = 0 .666666666710 ≅ .101010102 = .5 + .125 + .0313 + ..0078 = .664110 .101010102 = .1010_10102 = .AA16 = 10/16 + 10/256 = .664110 (Same as (b)). 1.14 ` 1.15 1.16 (a) 1001_0000 (b) 1s comp: 0110_1111 2s comp: 0111_0001 0000_0000 (c) 1s comp: 1111_1111 2s comp: 0000_0000 1101_1010 1s comp: 0010_0101 2s comp: 0010_0110 (d) 1010_1011 (e) 1s comp: 0101_0100 2s comp: 0101_0111 1010_0101 (f) 1s comp: 0101_1010 2s comp: 0101_1011 1111_1111 1s comp: 0000_0000 2s comp: 0000_0001 (a) 25,875,036 (b) 9s comp: 74,124,963 10s comp: 74,124,964 76,325,800 9s comp: 26,674,199 10s comp: 26,674,200 (c) 25,101,236 (d) 9s comp: 74,898,763 10s comp: 74,898,764 00000000 9s comp: 99999999 10s comp: 100000000 C3AF 15s comp: 3C50 16s comp: 3C51 C3AF: 1100_0011_1010_1111 1s comp: 0011_1100_0101_0000 2s comp: 0011_1100_0101_0001 = 3C51 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 6 1.17 (a) 6,473 – 5297 = 1176 5297 → 05297 →94702 (9s comp) → 94703 (10s comp) 6473 – 5297 = 6473 + 94703 = 101,176 (positive) Magnitude: 1,176 Result: 6,473 – 5297 = 1176 (b) 1,076 – 3,217 = -2,141 3,217 → 96,782 (9s comp) → 96,783 (10s comp) 1,076 – 3,217 = 1,076 + 96,783 = 97,858 (negative) Magnitude: 2,141 Result: 1,076 – 3,217 = -2,141 (c) 4,361 → 04361 → 95638 (9s comp) → 95639 (10s comp) 2043 – 4361 = 02043 + 95639 = 97682 (Negative) Magnitude: 2318 Result: 2043 – 6152 = -2318 (d) 745 → 00745 → 99254 (9s comp) → 99255 (10s comp) 1631 -745 = 01631 + 99255 = 0886 (Positive) Result: 1631 – 745 = 886 1.18 (a) 0_10110 (22) (b) 0_100110 1s comp: 1_01001 1s comp: 1_011001 with sign extension 2s comp: 1_01010 2s comp: 1_011010 0_10111 (23) 0_100010 Diff: 0_00001 (Positive) 1_111100 sign bit indicates that the result is negative Result: +1 0_000011 1s complement 0_000100 2s complement 0_000100 magnitude Check: 23-22 = +1 Result: -4 Check: 34 -38 = -4 (c) 0_110101 (d) 0_010101 1s comp: 1_001010 1s comp: 1_101010 with sign extension 2s comp: 1_001011 2s comp: 1_101011 0_001001 0_101000 1_010100 (negative) 0_010011 sign bit indicates that the Diff: result is positive 0_101011 (1s comp) Result: 1910 0_101100 (2s complement) Check: 40 – 21 = 1910 101100 (magnitude) -4410 (result) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 7 1.19 +9286 → 009286; +801 → 000801; -9286 → 990714; -801 → 999199 (a) (+9286) + (_801) = 009286 + 000801 = 010087 (b) (+9286) + (-801) = 009286 + 999199 = 008485 (c) (-9286) + (+801) = 990714 + 000801 = 991515 (d) (-9286) + (-801) = 990714 + 999199 = 989913 1.20 +49 → 0_110001 (Needs leading zero extension to indicate + value); +29 → 0_011101 (Leading 0 indicates + value) -49 → 1_001110 + 0_000001→ 1_001111 -29 → 1_100011 (sign extension indicates negative value) (a)(+29) + (-49) = 0_011101 + 1_001111 = 1_101100 (1 indicates negative value.) Magnitude = 0_010011 + 0_000001 = 0_010100 = 20; Result (+29) + (-49) = -20 (b) (-29) + (+49) = 1_100011 + 0_110001 = 0_010100 (0 indicates positive value) (-29) + (+49) = +20 (c) Must increase word size by 1 (sign extension) to accomodate overflow of values: (-29) + (-49) = 11_100011 + 11_001111 = 10_110010 (1 indicates negative result) Magnitude: 01_001110 = 7810 Result: (-29) + (-49) = -7810 1.21 +9742 → 009742 → 990257 (9’s comp) → 990258 (10s) comp +641 → 000641 → 999358 (9’s comp) → 999359 (10s) comp (a) (+9742) + (+641) → 010383 (b)(+9742) + (-641) →009742 + 999359 = 009101 Result: (+9742) + (-641) = 9101 (c) -9742) + (+641) = 990258 + 000641 = 990899 (negative) Magnitude: 009101 Result: (-9742) + (641) = -9101 (d) (-9742) + (-641) = 990258 + 999359 = 989617 (Negative) Magnitude: 10383 Result: (-9742) + (-641) = -10383 1.22 6,514 BCD: 0110_0101_0001_0100 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 8 ASCII: 0_011_0110__0_011_0101__1_011_0001__1_011_0100 ASCII: 0011_0110__0011_0101__1011_0001__1011_0100 3,274 BCD: 0011_0010_0111_0100 ASCII: 0011_0011_1011_0010_1011_0111_1011_0100 1.23 0111 1001 0001 ( 791) 0110 0101 1000 (+658) 1101 1110 1001 0110 0110 0001 0011 0100 0001 0001 0001 0100 0100 1001 (1,449) 1.24 (a) See text (b) 6 4 2 1 Decimal 0 0 0 0 0 1 0 0 0 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 5 0 1 0 1 6 0 1 1 0 0 1 1 1 7 8 1 0 1 0 1 0 1 1 9 1.25 (a) 6,42810 BCD: 0110_0100_0010_1000 (b) Excess-3: 1001_0111_0101_1011 (c) (d) 1.26 2421: 2421: 1100_0100_0010_1110 0110_0100_1000_1110 6311: 1000_0110_0010_1011 6,428 9s Comp: 3,571 6 4 2 8 2421 code: 0011_1011_0111_0001 1.25(c): 1s comp: 1100_0100_0010_1110 (2421 code – alternative #1) 0011_1011_1101_0001 (2421 code – alternative #2) 6 4 2 8 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 9 6,4282421 1s comp 0110_0100_1000_1110(2421 code alternative #2) 1001_1011_0111_0001 Match 5,736 9s Comp: 4,263 2421 code: 0100_0010_1100_0011 1s comp: 1011_1101_0011_1100 1.27 1.28 For a deck with 52 cards, we need 6 bits (25 = 32 < 52 < 64 = 26). Let the msb's select the suit (e.g., diamonds, hearts, clubs, spades are encoded respectively as 00, 01, 10, and 11. The remaining four bits select the "number" of the card. Example: 0001 (ace) through 1011 (9), plus 101 through 1100 (jack, queen, king). This a jack of spades might be coded as 11_1010. (Note: only 52 out of 64 patterns are used.) G (dot) (space) B o o l e 11000111_11101111_01101000_01101110_00100000_11000100_11101111_11100101 1.29 Steve Jobs 1.30 73 F4 E5 76 E5 4A EF 62 73 73: 0_111_0011 s F4: 1_111_0100 t E5: 1_110_0101 e 76: 0_111_0110 v E5: 1_110_0101 e 4A: 0_100_1010 j EF: 1_110_1111 o 62: 0_110_0010 b 73: 0_111_0011 s Even parity 1.31 62 + 32 = 94 printing characters; 34 special characters 1.32 Complement bit 6 (from the right) 1.33 (a) 897 1.34 ASCII for decimal digits with even parity: (b) 564 (c) 871 (d) 2,199 (0): 00110000 (1): 10110001 (2): 10110010 (4): 10110100 (5): 00110101 (6): 00110110 (8): 10111000 (9): 00111001 (3): 00110011 (7): 10110111 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 10 CHAPTER 2 2.1 (a) xyz x+y+z 000 001 010 011 100 101 110 111 0 1 1 1 1 1 1 1 (x + y + z)' x' 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 y' z' x' y' z' xyz (xyz) (xyz)' x' y' z' x' + y' + z' 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 000 001 010 011 100 101 110 111 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 0 (b) (c) xyz x + yz (x + y) (x + z) (x + y)(x + z) xyz x(y + z) xy xz xy + xz 000 001 010 011 100 101 110 111 0 0 0 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 000 001 010 011 100 101 110 111 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 (c) 2.2 (d) xyz x y+z x + (y + z) (x + y) (x + y) + z xyz yz x(yz) xy (xy)z 000 001 010 011 100 101 110 111 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 000 001 010 011 100 101 110 111 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 (a) xy + xy' = x(y + y') = x (b) (x + y)(x + y') = x + yy' = x(x +y') + y(x + y') = xx + xy' + xy + yy' = x (c) xyz + x'y + xyz' = xy(z + z') + x'y = xy + x'y = y (d) (x + y)'(x' + y')' = (x'y')(xy) = (x'y')(yx) = x'(y'y)x = 0 (e)(a + b + c')(a'b' + c) = aa'b' + ac + ba'b' + bc + c'a'b' + c'c = ac + bc +a'b'c' .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 11 (f) a'bc + abc' + abc + a'bc' = a'b(c + c') + ab(c + c') = a'b + ab = (a' + a)b = b 2.3 (a) xyz + x'y + xyz' = xy + x'y = y (b) x'yz + xz = (x'y + x)z = z(x + x')(x + y) = z(x + y) (c) (x + y)'(x' + y') = x'y'(x' + y') = x'y' (d) xy + x(wz + wz') = x(y +wz + wz') = x(w + y) (e) (yz' + x'w)(xy' + zw') = yz'xy' + yz'zw' + x'wxy' + x'wzw' = 0 (f) (x' + z')(x + y' + z') = x'x + x'y' + x'z' + z'x + z'y' + z'z' = x'y' + x'z' + xz' + y'z' = z' + y'(x' + z') = z' + y'z' + x'y' = z' + x'y' 2.4 (a) A'C' + ABC + AC' = C' + ABC = (C + C')(C' + AB) = AB + C' (b) (B'C' + D)' + D + BC + AD = (B'C')'D' + D + BC + AD =[(B + C)D' + D] + BC + AD = = (D + D')(D + B + C) + BC + AD = D + AD + B + BC + C = D(1 + A) + B(1 + C) + C =B+C+D (c) A'B(D' + C'D) + B(A + A'CD) = B(A'D' + A'C'D + A + A'CD) = B(A'D' + A + A'D(C + C') = B(A + A'(D' + D)) = B(A + A') = B (d) (A' + C)(A' + C')(A + B + C'D) = (A' + CC')(A + B + C'D) = A'(A + B + C'D) = AA' + A'B + A'C'D = A'(B + C'D) (e) ABC'D + A'BD + ABCD = AB(C + C')D + A'BD = ABD + A'BD = BD 2.5 (a) x y Fsimplified F (b) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 12 x y Fsimplified F (c) x y z Fsimplified F (d) A B 0 Fsimplified F (e) x y z Fsimplified F (f) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 13 x y z F Fsimplified 2.6 (a) A B C F Fsimplified (b) x y z F Fsimplified (c) x y F Fsimplified .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 14 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 15 (d) w x y z F Fsimplified (e) A B C D Fsimplified = 0 F (f) w x y z F Fsimplified 2.7 (a) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 16 A B C D F Fsimplified (b) w x y z F Fsimplified (c) A B C D F Fsimplified (d) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 17 A B C D F Fsimplified .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 18 (e) A B C D F Fsimplified 2.8 F' = (wx + yz)' = (wx)'(yz)' = (w' + x')(y' + z') FF' = wx(w' + x')(y' + z') + yz(w' + x')(y' + z') = 0 F + F' = wx + yz + (wx + yz)' = A + A' = 1 with A = wx + yz 2.9 (a) F' = (xy' + x'y)' = (xy')'(x'y)' = (x' + y)(x + y') = xy + x'y' (b) F' = [(a + c) (a + b')(a' + b + c')]' = (a + c)' + (a + b')' + (a' + b + c')' =a'c' + a'b + ab'c (c) F' = [z + z'(v'w + xy)]' = z'[z'(v'w + xy)]' = z'[z'v'w + xyz']' = z'[(z'v'w)'(xyz')'] = z'[(z + v + w') +( x' + y' + z)] = z'z + z'v + z'w' + z'x' + z'y' +z' z = z'(v + w' + x' + y') 2.10 (a) F1 + F2 = Σ m1i + Σm2i = Σ (m1i + m2i) (b) 2.11 F1 F2 = Σ mi Σmj where mi mj = 0 if i ≠ j and mi mj = 1 if i = j (a) F(x, y, z) = Σ(1, 4, 5, 6, 7) (b)F(a, b, c) = Σ(0, 2, 3, 4, 5, 7) F = xy + xy' + y'z F = ac + b'c' = Σ(0, 2, 3, 4, 5, 7) xyz F abc F 000 001 010 011 100 101 110 111 0 1 0 0 1 1 1 1 000 001 010 011 100 101 110 111 1 0 1 1 1 1 0 1 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 19 A = 1011_0001 B = 1010_1100 2.12 (a) (b) (c) (d) (e) 2.13 A AND B = 1010_0000 A OR B = 1011_1101 A XOR B = 0001_1101 NOT A = 0100_1110 NOT B = 0101_0011 (a) u x y z (u + x') Y = [(u + x')(y' + z)] (y' + z) (b) u x y x Y = (u xor y)' + x (u xor y)' (c) u x y z (u'+ x') Y = (u'+ x')(y + z') (y + z') (d) u x y z u(x xor z) Y = u(x xor z) + y' y' (e) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 20 u x y z u yz Y = u + yz +uxy uxy (f) u x y Y = u + x + x'(u + y') x'(u + y') (u + y') 2.14 (a) x y z F =xy + x'y' + y'z (b) x y z F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' (c) x y z F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 21 (d) x y z F = xy + x'y' + y'z = [(xy)' (x'y')' (y'z)']' (e) x y z F = xy + x'y' + y'z = (x' + y')' + (x + y)' + (y + z')' 2.15 (a) T1 = A'B'C' + A'B'C + A'BC' = A'B'(C' + C) +A'C'(B' + B) = A'B' +A'C' = A'(B' + C') (b) T2 =T1' = A'BC + AB'C' + AB'C + ABC' + ABC = BC(A' + A) + AB'(C' + C) + AB(C' + C) = BC + AB' + AB = BC + A(B' + B) = A + BC ∑(3, 5, 6, 7) = Π(0,1, 2, 4) T1 = A'B'C' + A'B'C + A'BC' A'B' A'C' T2 = A'BC + AB'C' + AB'C + ABC' + ABC AC' AC T1 = A'B' A'C' = A'(B' + C') BC T2 =AC' + BC + AC = A+ BC .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 22 2.16 (a) F(A, B, C) = A'B'C' + A'B'C + A'BC' + A'BC + AB'C' + AB'C + ABC' + ABC = A'(B'C' + B'C + BC' + BC) + A((B'C' + B'C + BC' + BC) = (A' + A)(B'C' + B'C + BC' + BC) = B'C' + B'C + BC' + BC = B'(C' + C) + B(C' + C) = B' + B = 1 (b)F(x1, x2, x3, …, xn) = Σmi has 2n/2 minterms with x1 and 2n/2 minterms with x'1, which can be factored and removed as in (a). The remaining 2n-1 product terms will have 2n-1/2 minterms with x2 and 2n-1/2 minterms with x'2, which and be factored to remove x2 and x'2. continue this process until the last term is left and xn + x'n = 1. Alternatively, by induction, F can be written as F = xnG + x'nG with G = 1. So F = (xn + x'n)G = 1. .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 23 2.17 (a) = Σ(3, 5, 6, 7, 11, 13, 14, 15) F' = Σ(0, 1, 2, 4, 8, 9, 10, 12) F = Π(0, 1, 2, 4, 8, 9, 10, 12) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 (b) F = (b + cd)(c + bd) = bc + bd + cd + bcd F 0 0 0 1 0 1 1 1 0 0 0 1 0 1 1 1 (cd + b'c + bd')(b + d) = bcd + bd' + cd + b'cd = cd + bd' = Σ (3, 4, 7, 11, 12,14, 15) = Π (0, 1, 2, 5, 6, 8, 9, 10, 13) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 0 0 0 1 1 0 0 1 0 0 0 1 1 0 1 1 (c) (c' + d)(b + c') = bc' + c' + bd + c'd = (c' + bd) = Σ (0, 1, 4, 5, 7, 8, 12, 13, 15) = Π (2, 3, 6, 9, 10, 11, 14) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 24 (d) bd' + acd' + ab'c + a'c' = Σ (0, 1, 4, 5, 10, 11, 14) F' = Σ (2, 3, 6, 7, 8, 9, 12, 13, 15) F = Π (0, 2, 3, 6, 7, 8, 12, 13, 15) abcd 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 F 1 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 25 2.18 (a) wx y z F 00 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 10 0 0 10 0 1 10 1 0 10 1 1 11 0 0 11 0 1 11 1 0 11 1 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 F = xy'z + x'y'z + w'xy + wx'y + wxy F = Σ(1, 5, 6, 7, 9, 10 11, 13, 14, 15 ) (b) x y' z x' y' z w' x y w x' y w x y 5 – Three-input AND gates 2 – Three-input OR gates Alternative: 1 – Five-input OR gate 4 – Inverters F (c) F = xy'z + x'y'z + w'xy + wx'y + wxy = y'z + xy + wy = yʹz + y(w + x) (d) F = y'z + yw + yx) = Σ(1, 5, 9, 13 , 10, 11, 13, 15, 6, 7, 14, 15) = Σ(1, 5, 6, 7, 9, 10, 11, 13, 14, 15) (e) y' z x w y F 1 – Inverter, 2 – Two-input AND gates, 2 – Two-input OR gates .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 26 F = B'D + A'D + BD 2.19 ABCD ABCD ABCD -B'-D 0001 = 1 0011 = 3 1001 = 9 1011 = 11 A'–D 0001 = 1 0011 = 3 0101 = 5 0111 = 7 -B-D 0101 = 5 0111 = 7 1101 = 13 1111 = 15 F = Σ(1, 3, 5, 7, 9, 11,13, 15) = Π(0, 2, 4, 6, 8, 10, 12, 14) 2.20 (a) F(A, B, C, D) = Σ(2, 4, 6, 8, 12, 14) F'(A, B, C, D) = Σ(0, 1, 3, 5, 7, 9, 10, 11, 13, 15) F(A, B, C, D) = Π( 0, 1, 3, 5, 7, 9, 10, 11, 13, 15) (b) F(x, y, z) = Π(3, 5, 7) F' = Π(0, 1, 2, 4, 6) F = Σ (0, 1, 2, 4, 6) 2.21 (a)F(x, y, z) = Σ(1, 3, 5) = Π(0, 2, 4, 6, 7) (b) F(A, B, C, D) = Π(3, 5, 8, 11) = Σ(0, 1, 2, 4, 6, 7, 9, 10, 12, 13, 14, 15) (c) F(x, y, z) = Π(0, 2, 4, 6) = Σ(1, 3, 5, 7) (d) F(w, x, y, z) = Σ(1, 3, 5, 7, 9) = Π(0, 2, 4, 6, 8, 10, 11, 12, 13, 14, 15) 2.22 (a) (u + xw)(x + u'v) = ux + uu'v + xxw + xwu'v = ux + xw + xwu'v = ux + xw = x(u + w) = ux + xw (SOP form) = x(u + w) (POS form) (b) x' + x(x + y')(y + z') = x' + x(xy + xz' + y'y + y'z') = x' + xy + xz' + xy'z' = x' + xy +xz' (SOP form) = (x' + y + z')(POS form) 2.23 BC' +ABC + ACD + BD (a) A B A' C B' D C' D' BC' ABC .Digital Design With An Introduction to the Verilog HDL, VHDL,ACD and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . BD All rights reserved. 27 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 28 (b) (A + B)(C + D)(A' + B + D) A B C D F (c) (AB + A'B')(CD' + C'D) A B C D F (d) A + CD + (A + D')(B' + D) A B A' C B' D C' D' F 2.24 x ⊕ y = x'y + xy' and (x ⊕ y)' = (x + y')(x' + y) Dual of x'y + xy' = (x' + y)(x + y') = (x ⊕ y)' .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 29 2.25 (a) x| y = xy' ≠ y | x = x'y Not commutative (x | y) | z = xy'z' ≠ x | (y | z) = x(yz')' = xy' + xz Not associative (b) (x ⊕ y) = xy' + x'y = y ⊕ x = yx' + y'x Commutative (x ⊕ y) ⊕ z = ∑(1, 2, 4, 7) = x ⊕ (y ⊕ z) Associative 2.26 NAND (Positive logic) Gate xy z xy z xy z LL LH HL HH H H H L 00 01 10 11 1 1 1 0 11 10 01 00 0 0 0 1 NOR (Positive logic) Gate 2.27 NOR (Negative logic) NAND (Negative logic) xy z xy z xy z LL LH HL HH H L L L 00 01 10 11 1 0 0 0 11 10 01 00 0 1 1 1 f1 = a'b'c' + a'bc' + a'bc + ab'c' + abc = a'c' + bc + a'bc' + ab'c' f2 = a'b'c' + a'b'c + a'bc + ab'c' + abc = a'b' + bc + ab'c' .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 30 a' b' a' a' b c' a' b c a' b c a b c a' b' c a' b c a b' c a' c' b f1 f2 c a' b c' a b' c' a' b' b c a b' c' f1 f2 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 31 2.28 (a)y = a(bcd)'e = a(b' + c' + d')e y = a(b' + c' + d')e = ab’e + ac’e + ad’e = Σ( 17, 19, 21, 23, 25, 27, 29) a bcde y a bcde y 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 0 1000 0 1001 0 1010 0 1011 0 1100 0 1101 0 1110 0 1111 1 1000 1 1001 1 1010 1 1011 1 1100 1 1101 1 1110 1 1111 (b) y1 = a ⊕ (c + d + e)= a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef y1 = a (c + d + e) = a'(c + d +e) + a(c'd'e') = a'c + a'd + a'e + ac'd'e' y2 = b'(c + d + e)f = b'cf + b'df + b'ef a'-c–001000 = 8 001001 = 9 001010 = 10 001011 = 11 a'–d-000100 = 8 000101 = 9 000110 = 10 000111 = 11 a'—e000010 = 2 000011 = 3 000110 = 6 000111 = 7 a-c'd'e'100000 = 32 100001 = 33 110000 = 34 110001 = 35 001100 = 12 001101 = 13 001110 = 14 001111 = 15 001100 = 12 001101 = 13 001110 = 14 001111 = 15 001010 = 10 001011 = 11 001110 = 14 001111 = 15 -b' c–f -b' -d-f -b' –ef 011000 = 24 011001 = 25 011010 = 26 011011 = 27 010100 = 20 010101 = 21 010110 = 22 010111 = 23 010010 = 18 010011 = 19 010110 = 22 010111 = 23 011100 = 28 011101 = 29 011110 = 30 011111 = 31 011100 = 28 011101 = 29 011110 = 30 011111 = 31 011010 = 26 011001 = 27 011110 = 30 011111 = 31 001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47 001001 = 9 001011 = 11 001101 = 13 001111 = 15 101001 = 41 101011 = 43 101101 = 45 101111 = 47 000011 = 3 000111 = 7 001011 = 11 001111 = 15 100011 = 35 100111 = 39 101011 = 51 101111 = 55 .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 32 y1 = Σ (2, 3, 6, 7, 8, 9, 10 ,11, 12, 13, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 ) y2 = Σ (3, 7, 9, 13, 15, 35, 39, 41, 43, 45, 47, 51, 55) 2.29 ab cdef y1 y 2 ab cdef y1 y2 ab cdef y1 y2 ab cdef y1 y2 00 0000 00 0001 00 0010 00 0011 00 0100 00 0101 00 0110 00 0111 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 01 0000 01 0001 01 0010 01 0011 01 0100 01 0101 01 0110 01 0111 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 10 0000 10 0001 10 0010 10 0011 10 0100 10 0101 10 0110 10 0111 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 1 11 0000 11 0001 11 0010 11 0011 11 0100 11 0101 11 0110 11 0111 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 00 1000 00 1001 00 1010 00 1011 00 1100 00 1101 00 1110 00 1111 1 1 1 1 1 1 1 1 0 1 0 0 0 1 0 1 01 1000 01 1001 01 1010 01 1011 01 1100 01 1101 01 1110 01 1111 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10 1000 10 1001 10 1010 10 1011 10 1100 10 1101 10 1110 10 1111 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 11 1000 11 1001 11 1010 11 1011 11 1100 11 1101 11 1110 11 1111 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x'y' + x'z + x'z' = x'z' + y'z' + x'z x'y' + x' = x' + y'z' x' = x' + y'z' FALSE 2.30 (b + d)(a' + b' + c) = a'b + bb' + bc + a'd + b'd + cd = a'b + bc + a'd + b'd + cd 2.31 a'b + a'c' + abc = a'bc + a'bc' + a'bc' + a'b'c' + abc = Σ (m3 + m2 + m0 + m7) (a'b + a'c' + abc)' = Σ (m1 + m4 + m5 + m6) (a'b + a'c' + abc) = Π (M1 + M4 + M5 + M6) (a'b + a'c' + abc) = (a' + b' + c)(a + b' + c')(a + b' + c)(a + b + c') 2.32 a b c a f g b c f g .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 33 2.33 a b a f g b f g .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 34 Chapter 3 3.1 y yz x 00 m0 11 10 m3 m0 1 m4 1 00 m2 1 0 x 01 m1 m5 1 m7 y yz x m6 1 m5 1 00 m0 1 0 11 m3 1 m4 x 01 m1 10 y 00 m0 1 m7 1 yz x m2 1 m5 1 m6 z F = z' + xy' y yz m7 1 z F = xy' + x'z' x 10 m2 1 m4 x 11 m3 1 0 1 01 m1 01 m6 m4 x m3 1 0 1 11 m1 10 m2 1 m5 m7 1 m6 1 1 z F = x'z + yz + x'y z F = x' + y'z 3.2 x 00 0 x y yz 1 m0 1 m4 m1 m5 11 m3 1 m7 1 00 m0 01 11 m1 m3 m4 1 m6 x m5 1 m7 1 z F = xy' + x'y 1 x 10 m1 m4 m5 x m3 1 m6 1 1 y yz 00 01 11 m1 m3 1 m4 1 10 m2 1 m7 0 1 m6 1 11 z F = y + x'z m0 m2 01 m0 (b) 1 0 x 0 y yz 00 m2 1 y yz x 10 z F = x'y' + xz (a) x 01 10 m2 1 m7 m5 1 1 m6 1 1 z F=y+z .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved. 35 (c) x (d) y yz 00 m0 0 11 10 m3 m5 m7 m6 1 00 11 01 m1 m3 m4 x m5 1 10 m2 1 0 1 1 1 y yz m0 m2 1 m4 x 01 m1 x m7 1 m6 1 1 1 z z F = z' F=x+yz (e) (f) 3.3 x y yz 00 m0 0 x 1 m4 1 m5 m7 10 m2 m6 1 1 1 x 00 0 01 m1 11 m3 1 m4 1 m5 1 m7 1 x 10 1 m4 x 1 m5 11 m3 1 m7 1 10 m2 1 m6 z F = x'y' + yz + x'yz' F = x' + yz 00 m0 01 m1 11 m3 10 m2 1 m4 1 m5 1 m7 m6 1 z F = x'yz + xy'z' + xy'z F = x'yz + xy' z F = x'y + yz' + y'z' F = = x' y + z' (c) 1 01 m1 yz 0 1 m6 00 m0 (b) m2 1 y yz 0 y yz m0 x 11 m3 z F =xy + x'y'z' + x'yz' F = xy + x' z' (a) x 01 m1 x (d) .Digital Design With An Introduction to the Verilog HDL, VHDL, and SystemVerilog, Sixth Edition – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2017 . All rights reserved.